1. Technical Field
The present disclosure relates to a base cell for an Engineering Change Order (ECO) implementation and, more particularly but non exclusively, relates to a mask programmable base cell for Engineering Change Order (ECO) post-silicon implementation, and the following description refers to this application field only to simplify the explanation.
2. Description of the Related Art
As it is well known, demands of consolidating functions and applications from printed circuit board to a single chip are growing stronger. These demands have made Integrated Circuit (IC) scales and designs increasingly complex and time consuming. For this reason, Computer-Aided Design (CAD) has become a necessary tool to speed up and improve the quality of IC design. In particular, physical layout takes up a major portion of the cycle of designing an Application Specific Integrated Circuit (ASIC).
In creating a physical layout of an ASIC, a computer layout may be first generated generally by arranging a number of individual blocks or “logic cells” based on designated schematics. The functionality and design of individual logic cells may be predetermined and stored on a computer system as a standardized cell design. Such cell design techniques can save time in design cycle, as it may be no longer necessary for an IC designer to custom design each individual gate and transistor in an integrated circuit. Rather, the circuit designer breaks down a new circuit design into a number of known (or new) cell designs and then combines these cells appropriately to generate a circuit layout that performs a desired function.
Each of the logic cells contains a number of terminals for implementing into the IC.
To release the layout to mask making for semiconductor processing, the data is loaded in a “tape,” and it is given to a mask shop, the so-called “tape-out phase.”
To tape-out such a computer layout, commercial place-and-route CAD tools are used. More particularly, place-and-route CAD programs are used to arrange logic cells and other elements to optimize their interconnections, overall size, and to define the routing region and select channels to connect the logic cells and elements.
A place-and-route CAD tool requires as input a predetermined number of predefined logic cell types (e.g., Inverter, NAND, NOR, XOR, Multiplexer, flip-flop, Decap, etc.) to implement the tasks mentioned above. In response, the place-and-route CAD tool outputs a computer layout.
Using the computer layout generated as a blueprint, a number of basic CMOS transistor layers, contact, and metal layers defining the elements and interconnections of the IC are created in silicon through a combination of semiconductor processes, including depositing, masking, and etching. When combined, these layers form the IC with the desired functionality.
Depending on the complexity of the ASIC, each circuit may involve multiple basic layers, multiple contacts, and multiple metal layers. This layer-patterns-release procedure is widely known as “tape-out.”
Following tape-out, for various reasons including design changes, modifications are subsequently required to delete as well as add logic elements and interconnections from the original design.
When this occurs, an Engineering Change Order (ECO) is generated to document the desired changes.
Next, the earlier generated computer layout is modified using the commercial place-and-route CAD tool to incorporate the desired changes.
Under conventional methods, extra logic cells, or filler cells, of different types are included in the original computer layout as reserves in case new elements are needed. However, due to limitations inherent in the software environment, the place-and-route CAD tool requires that these extra logic cells be of the predefined types and numbers.
Because the types of the logic cells are predefined as Inverter, NAND, NOR, XOR, Multiplexer, flip-flop, Decap, etc., modifications are limited to changing the logic cells connectivity. Such inflexibility may cause negative consequences.
For instance, in adding logic elements as required under an ECO, a logic cell of a certain type may not be available for implementing a desired function. As a result, either the desired function must be deleted or the process of generating a computer layout with the desired logic cells must be restarted and, of course, neither one of these options is desirable.
In addition, even if the correct type logic cells are available for adding, the layout engineer must still make the proper connections; however, because the locations of the logic cells are fixed, it is sometimes not possible to provide the desired connections given existing obstacles and various space constraints in the layout. Moreover, it is a painful and time-consuming task to identify the extra logic cells and provide the proper wiring to properly connect the added cells.
Because of the increasing complexity of the IC design and modification, the turn-around time to incorporate the desired ECO changes is generally high.
Many attempts to implement the desired ECO changes to a device layout design and to create a flexible ECO base cell have been made in order to obtain a shorter product life cycle and costs reduction.
A known solution is described in U.S. Patent Application Publication Number US 2005/0235240 in the name of Taiwan Semiconductor Manufacturing Co., Ltd. This patent application discloses an ECO base cell module, shown in the annexed FIG. 1.
The cell 100 has a virtual center line 102 with respect to which all patterns of material layers are mirrored in a symmetrical way. Moreover, the cell 100 includes an N-well 104 wherein one or more PMOS transistors may be formed and a P-well 106 wherein one or more NMOS transistors may be formed, a P+ implant region 110 that forms the source and drain regions for PMOS transistors, an N+ implant region 112 that forms the source and drain regions for NMOS transistors, a MOS channel region formed by a polysilicon layer 108 together with a gate oxide, an N-well pick-up region formed by the N+ implant 112 together with contacts 114 and a P-well pick-up region formed by the P+ implant 110 together with contacts 118. The cell 100 also includes a first power supply line VDD and a second power supply line VSS.
This known ECO base cell 100 has a same configuration as a standard logic cell and is alterable in at least one metal layer of the integrated structure forming it for realizing one or more connections to form a functional logic cell, like an Inverter, NAND, NOR, XOR, Multiplexer, flip-flop, de-coupling capacitors (Decap), etc.
In fact, in an original design, one or more logic cells (i.e., already configured cells) may be placed and connected through routing to form higher level functions, and one or more base cells (i.e., virgin cells) may also be placed in predetermined locations as fillers to prepare for future needed revisions.
During a design revision, the base cells can be transformed into logic or target cells through metal to silicon contacts, metal to polysilicon contacts, or other metal layer changes.
The modification of metal contact layers is a drawback of this known solution because it does not sufficiently reduce the costs and the fabrication time of the products. In addition, the base cell 100 as above described only allows the configuration of simple base cells, while the complex cells can be obtained only through the composition of these basic structures.
As a consequence, the construction of some complex cells, like three-state buffers, needs a very expensive implementation in terms of area occupation and an increase in the number of basic cells. This area increase reduces the flexibility of the ECO implementation and the number of logic cells available, increasing the routing resources needed in the ECO implementation, this being a very critical problem for design development.
The technical problem of the present disclosure is to provide a base cell layout for an Engineering Change Order (ECO) implementation having structural and functional features that provide a reduction in design revision time and costs, overcoming the limitations and drawbacks of the known solutions.